The invention relates to an integrated dynamic memory having a memory cell array with memory cells for storing a charge corresponding to an information bit. The invention further relates to a method for operating an integrated memory of this type.
Integrated memories, such as, for example, a dynamic random access memory (DRAM) use capacitors for storing charge. The charge state in the capacitor in each case represents an information bit.
A DRAM chip contains a matrix of memory cells that are arranged in rows and columns and that are addressed by word lines and bit lines. Reading data from the memory cells or writing data to the memory cells is realized by activating suitable word lines and bit lines.
The charge stored in the capacitor decreases over time on account of recombination and leakage currents. Before the charge has decreased to an indeterminate level below a specific threshold value, the capacitor charge must be refreshed. This operation is referred to as xe2x80x9crefreshxe2x80x9d. For this reason, these memory cells are called dynamic RAM (DRAM), in contrast to static RAMs (SRAM), which do not need refreshing.
The term retention time refers to that period of time for which a memory cell of a DRAM can retain the stored charge without falling below the threshold value. The refresh time, specifically the time between two refresh operations, must therefore be equal to or shorter than the retention time so that data losses do not occur.
The refreshing of the storage capacitors is generally controlled by an external module, for instance, the controller of a PC (Personal Computer) for all of the installed memory modules. If the memory modules have different refresh times, the weakest module with the shortest refresh time determines the refresh cycle for all of the modules. A refresh that is as infrequent as possible, that is to say a long refresh time, is advantageous since first the memory module is blocked during the refresh and is not available for other tasks, and second every refresh is associated with a charge transport and thus a current consumption. This has a disadvantageous effect particularly in the case of portable devices, whose rechargeable-battery operating time is critical.
A general problem in the case of the retention time of a semiconductor memory is due to the fact that the retention time is not an invariable constant, but rather can depend on the ambient and operating temperature, and also on the age of the module.
At the present time, this circumstance is taken into account by assuming a maximum operating temperature, for example 95xc2x0, which is composed for instance of a maximum specified external temperature of 70xc2x0 C. and an inherent heating proportion of 25xc2x0 C. The memory modules are then tested at this temperature and memory cells which did not satisfy the specification are replaced by redundant memory cells, or the refresh time is set so conservatively at delivery that the remaining memory cells have a retention time above the chosen refresh time up to the maximum temperature.
For a 128 Mbit memory module having 4096 rows, 64 ms, for example, is generally chosen as the refresh time. The chip is tested at the maximum operating temperature at 64 ms and the weak cells are eliminated in a customary manner by redundancy repairs. After a successful test of a module, it is then assumed that:
the retention time was set correctly by fuses/trimmer;
the retention is identical for volatile logic ones (xe2x80x9c1xe2x80x9d) and logic zeros (xe2x80x9c0xe2x80x9d);
the defective cells have been eliminated by redundancy activation;
the inherent chip heating does not increase in operation throughout the lifetime of the product;
the retention susceptibility does not increase or vary with respect to time, as in the case of the so-called xe2x80x9cvariable retention timexe2x80x9d;
the actually tested temperature at which the retention time was determined is known precisely.
These expectations for the most part represent simplified assumptions which, when not completely applicable, are compensated for, for example, by overtesting after production. Alternatively, these assumptions can lead to failures after a certain operating duration. This loss is unacceptable in particular in the case of high-reliability components, for example, in mainframe computers, in power station control and the like.
It is accordingly an object of the invention to provide an integrated dynamic memory which overcomes the above-mentioned disadvantages of the prior art apparatus of this general type.
In particular, it is an object of the invention to provide an integrated dynamic memory that when compared with conventional dynamic memories, has a small current consumption and/or is available for random read/write accesses for the longest possible proportion of time.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated dynamic memory including a memory cell array having a regular cell area with regular memory cells, a first test cell area with first test cells, and a second test cell area with second test cells. The regular memory cells, the first test cells and the second test cells are for storing a charge corresponding to an information bit. The integrated dynamic memory also includes: a control unit for refreshing charge contents of the regular memory cells with a first refresh time Tref; a control unit for refreshing charge contents of the first test cells with a second refresh time T1, and for refreshing charge contents of the second test cells with a third refresh time T2; and an evaluation unit for detecting memory cell defects in the first test cell area and in the second test cell area. The first refresh time Tref is shorter than the second refresh time T1; and the second refresh time T1 is shorter than the third refresh time T2.
The invention is thus based on the concept of functionally separating subareas of the memory cell array from the regular memory area and using them for monitoring and analyzing the retention time that is presently required. In this case, the invention assumes that the cells used for the retention analysis have the same production-dictated retention quality as the regular memory cell array and the underlying statistics are not significantly impaired by the limited number of cells used for the analysis.
Both assumptions are generally satisfied well, since the cell areas used for the retention analysis originate from the same memory cell array as the regular memory cells. Moreover, after the redundancy activation, there are generally still sufficiently many redundant memory cells available which can be utilized for the retention analysis with adequate statistics.
Preferably, the evaluation unit has a device for altering the refresh times Tref, T1 and T2 on the basis of detected memory cell defects. This makes it possible to adapt the refresh time Tref to instantaneous conditions depending on the result of the memory tests carried out on the test cell areas, that is to say to increase or decrease the refresh time Tref. In this case, operation is carried out with a longer refresh time T1 in the first test cell area, and operation is carried out with an even longer refresh time T2 in the second test cell area.
If the evaluation of the memory test reveals that no memory cell defects occurred even at the longer refresh times T1 and T2, it can be concluded that the present operating conditions according to the temperature and the age of the module also permit the regular memory cells to be used with a longer refresh time Tref than presently set.
The refresh times Tref, T1 and T2 are expediently chosen such that the refresh time T1 is twice as long as Tref, and the refresh time T2 is twice as long as T1. The refresh time of the first test cell area thus differs by the factor 2, and that of the second test cell area by the factor 4, from the present setting for the regular memory areas.
This enables a reliable assessment of the appropriate refresh rate: this is because if the first memory cell area runs with the refresh time T1 without any memory defects, it can be concluded that the present, shorter refresh time Tref is in defect-free operation even with some safety margin. The first test cell area thus functions as a safety area whose defectless or defective operation allows conclusions about the operating state of the regular memory area.
As described in detail further below, the defect assessments of the first and second test cell areas together can be used not only to infer whether the regular memory cell area operates reliably, but also to determine the corrections that are necessary, if appropriate.
In a preferred refinement, the memory cell array of the integrated memory is organized in row lines and column lines and the regular cell area, the first test cell area and the second test cell area in each case include a number of row lines.
In this case, the row lines of the first and/or second cell area may be arranged next to one another at the edge of the regular memory cell area, or may be arranged between the row lines of the regular memory cell area. The first variant allows for simple access to the test cell areas arranged in a block-like manner, while in the second variant, it is ensured by the arrangement of the test cell rows between the regular memory cell rows in a particular manner that the test cell rows experience the same operating conditions and have the same physical properties as the regular memory cells. The retention behavior of the test cells is thus a true reflection of the retention behavior of the regular memory cells.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for operating the described integrated dynamic memory, which includes steps of: providing the integrated dynamic memory with a memory cell array having a regular cell area with regular memory cells, a first test cell area with first test cells, and a second test cell area with second test cells; providing the regular memory cells, the first test cells and the second test cells for storing a charge corresponding to an information bit; refreshing charge contents of the regular memory cells with a first refresh time Tref; writing test patterns to the first test cells and to the second test cells; refreshing charge contents of the first test cells with a second refresh time T1, and refreshing charge contents of the second test cells with a third refresh time T2; providing the first refresh time Tref being shorter than the second refresh time T2 and providing the second refresh time T2 being shorter than the third refresh time Tref; reading memory cell contents of the first test cell area and the second test cell area and detecting memory cell defects by comparing the memory cell contents with the test patterns that were written to the first test cells and to the second test cells; and checking the first refresh time Tref with regard to the memory cell defects that were detected in the first test cell area and in the second test cell area.
Preferably, in the method, after checking the first refresh time Tref with regard to detected memory cell defects:
the first refresh time Tref is lengthened, or is left unchanged after reaching a maximum refresh time Tmax if no memory cell defects are detected in the first and second test areas;
the first refresh time Tref is shortened, or is left unchanged after reaching a minimum refresh time Tmin if memory cell defects are detected in both the first and the second test areas; and
otherwise the first refresh time Tref is left unchanged.
In an expedient manner, after the first refresh time Tref is changed, the second and third refresh times of the test cell areas are correspondingly adapted. In particular, in the event of lengthening the first refresh time Tref, the second and third refresh times T1, T2 are lengthened, so that the first refresh time Tref is shorter than the second refresh time T1 and the second refresh time T1 is shorter than the third refresh time T2.
Equally, in the event of shortening the first refresh time Tref, the second and third refresh times T1, T2 are shortened, so that the first refresh time Tref is shorter than the second refresh time T1 and the second refresh time T1 is shorter than the third refresh time T2.
The operating method can then proceed as described above, only with changed refresh times. The refresh times can, of course, also be changed repeatedly one after the other or with a time interval, in order, for instance, to take account of further heating or cooling of the module.
Preferably, the refresh times Tref, T1 and T2 are doubled in the case of lengthening, and are halved in the case of shortening.
By way of example, the refresh times Tref, T1 and T2 may assume a value from the group 1 ms, 2 ms, 4 ms, 8 ms, 16 ms, 32 ms, 64 ms, 128 ms, 256 ms, 512 ms, 1024 ms, 2048 ms and 4096 ms. The minimum refresh time Tmin is then 1 ms and the maximum refresh time Tmax for the regular memory cells is 1024 ms. Of course, other values are also appropriate for the refresh times depending on the application and complexity of the memory module.
It is useful for the defect analysis if, in the event of memory cell defects being detected, the type of memory cell defects is ascertained, in particular whether only logic zeros, only logic ones, or both have failed.
During the operation of a plurality of the integrated dynamic memory modules described, the following method steps are carried out:
for each of the integrated memory modules, in response to a request signal from an external controller, the refresh time Tref thereof is determined and communicated to the controller;
the controller determines the shortest of the refresh times; and
the shortest refresh time that has been determined is subsequently used for refreshing each of the plurality of memory modules.
In a refinement of this method, for each of the integrated memory modules, the refresh times T1 and T2 of the first and second test cells are continually determined and stored in registers. The refresh times T1, T2 of all of the memory modules are read out by an external controller, and the controller decides, on the basis of the read out refresh times T1, T2, about outputting a request signal for determining the refresh times Tref of the memory modules.
In the self-refresh mode, by contrast, each memory module can execute its refresh mode without external control according to its own refresh time Tref, even if this refresh time differs from the refresh time of the other installed memory modules.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated dynamic memory and operating method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.